1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
Conventionally, a semiconductor chip having a super-junction MOSFET and a semiconductor chip having an insulated-gate bipolar transistor are connected in parallel, as shown in Patent Document 1, for example. Super junction is abbreviated as “SJ” in the following description. Furthermore, an insulated-gate bipolar transistor is abbreviated as “IGBT” in the following description. A conventional SJ-MOSFET structure is known that includes a p+ collector layer, as shown in Patent Document 2, for example. In addition, conventionally, an IGBT and an SJ-MOSFET are connected in parallel, as shown in Patent Document 3, for example.